1. Field of the Invention
The present invention relates to analog-to-digital converters and the like, and more particularly to a digital-to-analog converter of the resistor string type.
2. Description of the Background
FIG. 11, shows a recently proposed digital-to-aralog converter of the resistor string type which has been arranged on a wafer within, for instance, an analog-to-digital converter assembly of the successive-approximatior type. The digital-to-analog converter includes a string of 2.sup.n resistors r , . . . , r respectively, each with a substantially identical resistance value which are connected in series with each other between V.sub.ref.sup.+ and V.sub.ref.sup.- terminals of a reference voltage source to be applied with a reference voltage V.sub.ref thereto. This means that the resistors r , . . . , r divide the reference voltages V.sub.ref produce a series of divided voltages respectively at their common terminals p , . . . , p. The string of resistors r , . . . , r are divided into a plurality of resistor string units R , . . . , R and folded into a square array along a line direction in order to save the wafer and to lessen process variations. The digital-to-analog converter includes a plurality of row lead wires 100 , . . . , 100 which are arranged on the wafer respectively in parallel with the resistor string units R, . . . , R to selectively pick up the divided voltages from the common terminals p , . . . , p of the string of resistors r , . . . , r. A plurality of line lead wires 101 , . . . , 101 corresponding respectively to the resistors of the resistor string units R , . . . , R are also arranged to cross respectively the resistor string units R , . . . , R. In this case, the row and line lead wires 100 , . . . , 100 and 101, . . . , 101 are selected by row and line decoders 102 and 103, respective. Furthermore, each of a plurality of switching elements in the form of a Field Effect Transistor or FET is connectd between the corresponding common terminal p and the corresponding line lead wire 101. Then, each of switching elements 104 , . . . , 104 is turned on through the corresponding row lead wire 100 by the row decoder 102 to output the divided voltage from the corresponding common terminal p through the corresponding line lead wire 101 as a voltage to be successively compared with an analog input voltage.
In such a construction as described above, the resistors r , . . . , r are fabricated in P.sup.+ and N.sup.+ diffusing areas of the wafer. This means that due to the diffusing process for fabricating the string of resistors r , . . . , r, variations in resistance values of resistors r , . . . , r will be caused with an incline from the one resistor r corresponding to the most significant position to the other resistor r corresponding to the least significant position. From this aspect, it will be observed that an incline in variations of resistance values of resistors r , . . . , r along the line directior may be substantially cancelled owing to the folded arrangement of the string of resistors r , . . . , r, whereas an incline in variations of resistance values at each resistor string unit R along the row direction may not be cancelled. This means that resistance values of resistors r , . . . , r change with an incline from the left-side resistor string unit R to the right-side resistor string unit R. As a result, the output voltage from the digital-to-analog converter has a large deviate from an ideal value of V.sub.ref /2, as shown by a curved line a in FIG. 6, to cause an increased nonlinearity error.
In determining the most significant bit or MSB in the digital-to-analog converter of the successive-approximation type, an output voltage indicative of V.sub.ref /2 is compared with the analog input voltage. The next most significant bit is obtained by using another output voltage indicative of one of V.sub.ref /4 and 3 V.sub.ref /4 which is compared with the analog input voltage. In this instance, a settling time of the digital-to-analog converter is defined by the total of resistance values of resistors r between the corresponding terminal p and the ground and parasitic capacities such as junction capacities of the switching elements 104 and the like. Furthermore, a settling time from the output voltage indicative of V.sub.ref /2 to another output voltage indicative of V.sub.ref /4 or 3 V.sub.ref /4 is longer than that for determination of each of the remaining bits, because the output voltage indicative of V.sub.ref /2, V.sub.ref /4 or 3 V.sub.ref /4 is higher than that for each of the remaining bits. This means that the settling time for determination of the MSB substantially defines a time period required for analog-to-digital conversion in all the bits. Thus, for a decrease of the time period in the analog-to-digital conversion, it is inevitably required to decrease the settling time or resistance values in the string of resistors r, . . . , r. However, this causes an increase in area of the layout pattern for the string of resistors r, . . . , r and in its wiring resistance values, resulting in an increase of nonlinearity error in the digital-to-analog converter.